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| 14-Bit, 165 MSPS TxDAC D/A Converter AD9744* (R) FEATURES High Performance Member of Pin Compatible TxDAC Product Family Excellent Spurious-Free Dynamic Range Performance SFDR to Nyquist: 83 dBc @ 5 MHz Output 80 dBc @ 10 MHz Output 73 dBc @ 20 MHz Output SNR @ 5 MHz Output, 125 MSPS: 77 dB Twos Complement or Straight Binary Data Format Differential Current Outputs: 2 mA to 20 mA Power Dissipation: 135 mW @ 3.3 V Power-Down Mode: 15 mW @ 3.3 V On-Chip 1.2 V Reference CMOS Compatible Digital Interface 28-Lead SOIC, 28-Lead TSSOP, and 32-Lead LFCSP Packages Edge-Triggered Latches APPLICATIONS Wideband Communication Transmit Channel: Direct IF Base Stations Wireless Local Loop Digital Radio Link Direct Digital Synthesis (DDS) Instrumentation GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM 3.3V REFLO +1.2V REF REFIO FS ADJ DVDD DCOM CLOCK CLOCK SEGMENTED SWITCHES LSB SWITCHES 150pF AVDD CURRENT SOURCE ARRAY ACOM 0.1 F AD9744 RSET 3.3V IOUTA IOUTB MODE LATCHES DIGITAL DATA INPUTS (DB13-DB0) SLEEP The AD9744 is a 14-bit resolution, wideband, third generation member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9744 offers exceptional ac and dc performance while supporting update rates up to 165 MSPS. The AD9744's low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 60 mW with a slight degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 15 mW. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. *Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. Edge-triggered input latches and a 1.2 V temperature compensated band gap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support 3 V CMOS logic families. PRODUCT HIGHLIGHTS 1. The AD9744 is the 14-bit member of the pin compatible TxDAC family, which offers excellent INL and DNL performance. 2. Data input supports twos complement or straight binary data coding. 3. High speed, single-ended CMOS clock input supports 165 MSPS conversion rate. 4. Low power: Complete CMOS DAC function operates on 135 mW from a 2.7 V to 3.6 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. On-chip voltage reference: The AD9744 includes a 1.2 V temperature compensated band gap voltage reference. 6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD9744-SPECIFICATIONS DC SPECIFICATIONS Parameter RESOLUTION DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance (Ext. Reference) Small Signal Bandwidth TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD CLKVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD)4 Clock Supply Current (ICLKVDD) Supply Current Sleep Mode (IAVDD) Power Dissipation4 Power Dissipation5 Power Supply Rejection Ratio--AVDD6 Power Supply Rejection Ratio--DVDD6 OPERATING RANGE 1 (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.) Min 14 -5 -3 -0.02 -0.5 -0.5 2 -1 0.8 0.5 +5 +3 +0.02 +0.5 +0.5 20 +1.25 Typ Max Unit Bits LSB LSB % of FSR % of FSR % of FSR mA V kW pF V nA V MW MHz ppm of FSR/C ppm of FSR/C ppm of FSR/C ppm/C 0.1 0.1 100 5 1.14 1.20 100 1.26 0.1 1 0.5 0 50 100 50 1.25 2.7 2.7 2.7 3.3 3.3 3.3 33 8 5 5 135 145 3.6 3.6 3.6 36 9 6 6 145 +1 +0.04 +85 -1 -0.04 -40 V V V mA mA mA mA mW mW % of FSR/V % of FSR/V C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS, is 32 times the I REF current. 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at f CLOCK = 25 MSPS and f OUT = 1 MHz. 5 Measured as unbuffered voltage output with I OUTFS = 20 mA and 50 W RLOAD at IOUTA and IOUTB, f CLOCK = 100 MSPS and f OUT = 40 MHz. 6 5% power supply variation. Specifications subject to change without notice. -2- REV. A AD9744 DYNAMIC SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) (to 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA)2 Output Noise (IOUTFS = 2 mA)2 Noise Spectral Density3 AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLOCK = 25 MSPS; fOUT = 1.00 MHz 0 dBFS Output -6 dBFS Output -12 dBFS Output -18 dBFS Output fCLOCK = 65 MSPS; fOUT = 1.00 MHz fCLOCK = 65 MSPS; fOUT = 2.51 MHz fCLOCK = 65 MSPS; fOUT = 10 MHz fCLOCK = 65 MSPS; fOUT = 15 MHz fCLOCK = 65 MSPS; fOUT = 25 MHz fCLOCK = 165 MSPS; fOUT = 21 MHz fCLOCK = 165 MSPS; fOUT = 41 MHz Spurious-Free Dynamic Range within a Window fCLOCK = 25 MSPS; fOUT = 1.00 MHz; 2 MHz Span fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span fCLOCK = 65 MSPS; fOUT = 5.03 MHz; 2.5 MHz Span fCLOCK = 125 MSPS; fOUT = 5.04 MHz; 4 MHz Span Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 2.00 MHz fCLOCK = 65 MSPS; fOUT = 2.00 MHz fCLOCK = 125 MSPS; fOUT = 2.00 MHz Signal-to-Noise Ratio fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA Multitone Power Ratio (8 Tones at 400 kHz Spacing) fCLOCK = 78 MSPS; fOUT = 15.0 MHz to 18.2 MHz 0 dBFS Output -6 dBFS Output -12 dBFS Output -18 dBFS Output (TMIN to TMAX , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated, unless otherwise noted.) Min 165 11 1 5 2.5 2.5 50 30 -155 Typ Max Unit MSPS ns ns pV-s ns ns pA//Hz pA//Hz dBm/Hz 77 90 87 82 82 85 84 80 75 74 73 60 90 90 87 87 -86 -77 -77 -77 82 88 77 78 70 70 -77 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB dB dB dB dB dB 84 66 68 62 61 dBc dBc dBc dBc NOTES 1 Measured single-ended into 50 W load. 2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only. 3 Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone. Specifications subject to change without notice. REV. A -3- AD9744 DIGITAL SPECIFICATIONS Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (tLPW) CLK INPUTS2 Input Voltage Range Common-Mode Voltage Differential Voltage 1 (TMIN to TMAX , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.) Min 2.1 -10 -10 5 2.0 1.5 1.5 0 0.75 0.5 3 2.25 Typ 3 0 Max Unit V V mA mA pF ns ns ns V V V 0.9 +10 +10 1.5 1.5 NOTES 1 Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode. 2 Applicable to CLK+ and CLK- inputs when configured for differential or PECL clock input mode. Specifications subject to change without notice. DB0-DB13 tS CLOCK tH t LPW t PD t ST 0.1% 0.1% IOUTA OR IOUTB Figure 1. Timing Diagram -4- REV. A AD9744 ABSOLUTE MAXIMUM RATINGS* Parameter AVDD DVDD CLKVDD ACOM ACOM DCOM AVDD AVDD DVDD CLOCK, SLEEP Digital Inputs, MODE IOUTA, IOUTB REFIO, REFLO, FS ADJ CLK+, CLK-, CMODE Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to Min ACOM DCOM CLKCOM DCOM CLKCOM CLKCOM DVDD CLKVDD CLKVDD DCOM DCOM ACOM ACOM CLKCOM -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -3.9 -3.9 -3.9 -0.3 -0.3 -1.0 -0.3 -0.3 -65 Max +3.9 +3.9 +3.9 +0.3 +0.3 +0.3 +3.9 +3.9 +3.9 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 CLKVDD + 0.3 150 +150 300 Unit V V V V V V V V V V V V V V C C C THERMAL CHARACTERISTICS* Thermal Resistance 28-Lead 300-Mil SOIC JA = 55.9C/W 28-Lead TSSOP JA = 67.7C/W 32-Lead LFCSP JA = 32.5C/W *Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ORDERING GUIDE Model AD9744AR AD9744ARRL AD9744ARU AD9744ARURL7 AD9744ACP AD9744ACPRL7 AD9744-EB AD9744ACP-PCB Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 28-Lead 300-Mil SOIC 28-Lead 300-Mil SOIC 28-Lead TSSOP 28-Lead TSSOP 32-Lead LFCSP 32-Lead LFCSP Evaluation Board (SOIC) Evaluation Board (LFCSP) Package Options* R-28 R-28 RU-28 RU-28 CP-32 CP-32 *R = Small Outline IC; RU = Thin Shrink Small Outline Package; CP = Lead Frame Chip Scale Package CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9744 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A -5- AD9744 PIN CONFIGURATION 28-Lead SOIC and TSSOP (MSB) DB13 1 DB12 2 DB11 3 DB10 4 DB9 5 DB8 6 28 CLOCK 27 DVDD 26 DCOM 25 MODE 32-Lead LFCSP 32 DB8 31 DB9 30 DB10 29 DB11 28 DB12 27 DB13 (MSB) 26 DCOM 25 SLEEP DB7 1 DB6 2 DVDD 3 DB5 4 DB4 5 DB3 6 DB2 7 DB1 8 PIN 1 INDICATOR TOP VIEW 23 RESERVED DB7 7 (Not to Scale) 22 IOUTA DB6 8 DB5 9 DB4 10 DB3 11 DB2 12 DB1 13 (LSB) DB0 14 21 IOUTB 20 ACOM 19 NC 18 FS ADJ 17 REFIO 16 REFLO 15 SLEEP AD9744 24 AVDD AD9744 TOP VIEW 24 FS ADJ 23 REFIO 22 ACOM 21 IOUTA 20 IOUTB 19 ACOM 18 AVDD 17 AVDD NC = NO CONNECT NC = NO CONNECT PIN FUNCTION DESCRIPTIONS SOIC/TSSOP Pin No. 1 2-13 14 15 16 17 LFCSP Pin No. 27 28-32, 1, 2, 4-8 9 25 N/A 23 Mnemonic DB13 DB12-DB1 DB0 SLEEP Description 18 19 20 21 22 23 24 25 N/A 24 N/A 19, 22 20 21 N/A 17, 18 16 15 26 27 28 N/A N/A N/A N/A 10, 26 3 N/A 12 13 11 14 Most Significant Data Bit (MSB). Data Bits 12-1. Least Significant Data Bit (LSB). Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated if not used. REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to ACOM). Requires 0.1 mF capacitor to ACOM when internal reference activated. FS ADJ Full-Scale Current Output Adjust. NC No Internal Connection. ACOM Analog Common. IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. IOUTA DAC Current Output. Full-scale current when all data bits are 1s. RESERVED Reserved. Do Not Connect to Common or Supply. AVDD Analog Supply Voltage (3.3 V). MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. CMODE Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK-). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip). DCOM Digital Common. DVDD Digital Supply Voltage (3.3 V). CLOCK Clock Input. Data latched on positive edge of clock. CLK+ Differential Clock Input. CLK- Differential Clock Input. CLKVDD Clock Supply Voltage (3.3 V). CLKCOM Clock Common. -6- (LSB) DB0 9 DCOM 10 CLKVDD 11 CLK 12 CLK 13 CLKCOM 14 CMODE 15 MODE 16 REV. A AD9744 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Power Supply Rejection Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (or DNL) The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Settling Time DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Spurious-Free Dynamic Range The deviation of the output current from the ideal of zero is called the offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion (THD) The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Output Compliance Range THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Multitone Power Ratio The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift The spurious-free dynamic range containing multiple carrier tones of equal amplitude. It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. Temperature drift is specified as the maximum change from the ambient (25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per C. For reference drift, the drift is reported in ppm per C. 3.3V REFLO +1.2V REF 0.1 F REFIO FS ADJ RSET 2k 3.3V DVDD DCOM CLOCK DVDD DCOM RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR 50 SLEEP 150pF AVDD ACOM AD9744 PMOS CURRENT SOURCE ARRAY IOUTA MINI-CIRCUITS T1-1T IOUTB MODE 50 50 RHODE & SCHWARZ FSEA30 SPECTRUM ANALYZER SEGMENTED SWITCHES FOR DB13-DB5 LATCHES LSB SWITCHES CLOCK OUTPUT DIGITAL DATA TEKTRONIX AWG-2021 WITH OPTION 4 *AWG2021 CLOCK RETIMED SO THAT THE DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. Figure 2. Basic AC Characterization Test Set-Up (SOIC/TSSOP Packages) REV. A -7- AD9744-Typical Performance Characteristics 95 90 85 80 65MSPS 125MSPS 165MSPS (LFCSP) 95 90 85 80 SFDR (dBc) 95 90 85 -6dBFS SFDR (dBc) 80 75 70 65 60 55 50 45 0dBFS -6dBFS -12dBFS SFDR (dBc) 75 70 65 60 55 50 45 1 10 fOUT (MHz) 100 125MSPS (LFCSP) 165MSPS 75 70 65 60 55 50 45 0 5 10 0dBFS -12dBFS 15 20 25 0 5 10 15 20 25 30 35 40 45 fOUT (MHz) fOUT (MHz) TPC 1. SFDR vs. fOUT @ 0 dBFS TPC 2. SFDR vs. fOUT @ 65 MSPS TPC 3. SFDR vs. fOUT @ 125 MSPS 90 85 -6dBFS (LFCSP) 95 90 20mA 85 80 SFDR (dBc) 75 70 65 60 0dBFS -6dBFS 0dBFS (LFCSP) 95 90 85 80 SFDR (dBc) 80 75 SFDR (dBc) 70 65 60 65 55 50 45 0 10 20 40 30 fOUT (MHz) 50 60 -12dBFS -12dBFS (LFCSP) 65MSPS 75 70 65 60 55 50 125MSPS 165MSPS 10mA 5mA 55 50 45 0 5 10 15 20 25 45 -25 -20 -15 -10 -5 0 fOUT (MHz) AOUT (dBFS) TPC 4. SFDR vs. fOUT @ 165 MSPS TPC 5. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS TPC 6. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/11 95 165MSPS (LFCSP) 90 85 80 SFDR (dBc) SNR (dB) 80 20mA LFCSP 95 65MSPS (8.3,10.3) 90 165MSPS (22.6, 24.6) 85 80 65MSPS 125MSPS (LFCSP) 75 20mA SOIC 70 75 70 65 60 125MSPS 55 50 45 -25 -20 -15 -10 AOUT (dBFS) -5 0 165MSPS SFDR (dBc) 75 78MSPS (10.1, 12.1) 70 125MSPS (16.9, 18.9) 65 60 65 10mA LFCSP 10mA SOIC 5mA SOIC 5mA LFCSP 60 55 55 50 50 25 45 65 105 125 fCLOCK (MSPS) 85 145 165 45 -25 -20 -15 -10 -5 0 AOUT (dBFS) TPC 7. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/5 TPC 8. SNR vs. fCLOCK and IOUTFS @ fOUT = 5 MHz and 0 dBFS TPC 9. Dual-Tone IMD vs. AOUT @ fOUT = fCLOCK/7 -8- REV. A AD9744 1.5 1.0 0.8 95 90 85 80 SFDR (dBc) 75 70 65 34MHz 60 55 50 49MHz 19MHz 4MHz 1.0 0.6 0.4 ERROR (LSB) ERROR (LSB) 0.5 0.2 0 -0.2 -0.4 0 -0.5 -1.0 -1.5 0 4096 8192 CODE 12288 16384 -0.6 -0.8 -1.0 0 4096 8192 CODE 12288 16384 45 -40 -20 0 20 40 60 80 TEMPERATURE ( C) TPC 10. Typical INL TPC 11. Typical DNL TPC 12. SFDR vs. Temperature @ 165 MSPS, 0 dBFS 0 -10 -20 fCLOCK = 78MSPS fOUT = 15.0MHz SFDR = 79dBc AMPLITUDE = 0dBFS MAGNITUDE (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 0 fCLOCK = 78MSPS fOUT1 = 15.0MHz fOUT2 = 15.4MHz MAGNITUDE (dBm) SFDR = 77dBc AMPLITUDE = 0dBFS -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 MAGNITUDE (dBm) -30 -40 -50 -60 -70 -80 -90 -100 1 6 11 16 21 26 31 36 fCLOCK = 78MSPS fOUT1 = 15.0MHz fOUT2 = 15.4MHz fOUT3 = 15.8MHz fOUT4 = 16.2MHz SFDR = 75dBc AMPLITUDE = 0dBFS -100 1 6 11 16 21 26 31 36 FREQUENCY (MHz) 1 6 11 16 21 26 31 36 FREQUENCY (MHz) FREQUENCY (MHz) TPC 13. Single-Tone SFDR TPC 14. Dual-Tone SFDR TPC 15. Four-Tone SFDR -20 -30 -40 MAGNITUDE (dBm) -39.01dBm 29.38000000MHz CH PWR -19.26dBm ACP UP -64.98dB ACP LOW +0.55dB ALT1 UP -66.26dB ALT1 LOW -64.23dB -50 -60 -70 -80 -90 -100 -110 -120 CENTER 33.22MHz 3MHz C12 C12 C11 C11 CU1 CU1 CU2 CU2 C0 C0 SPAN 30MHz TPC 16. Two-Carrier UMTS Spectrum (ACLR = 64 dB) REV. A -9- AD9744 3.3V REFLO +1.2V REF VREFIO 0.1 F RSET 2k IREF 3.3V REFIO FS ADJ DVDD DCOM CLOCK CLOCK SLEEP DIGITAL DATA INPUTS (DB13-DB0) SEGMENTED SWITCHES FOR DB13-DB5 LATCHES LSB SWITCHES 150pF AVDD ACOM AD9744 PMOS CURRENT SOURCE ARRAY IOUTA IOUTB IOUTB MODE VDIFF = VOUTA - VOUTB IOUTA VOUTB RLOAD 50 VOUTA RLOAD 50 Figure 3. Simplified Block Diagram (SOIC/TSSOP Packages) FUNCTIONAL DESCRIPTION REFERENCE OPERATION Figure 3 shows a simplified block diagram of the AD9744. The AD9744 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current source array capable of providing up to 20 mA of full-scale current (IOUTFS). The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an MSB current source. The remaining LSBs are binary weighted fractions of the middle bits current sources. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the DAC's high output impedance (i.e., >100 kW). All of these current sources are switched to one or the other of the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on the architecture that was pioneered in the AD9764 family, with further refinements to reduce distortion contributed by the switching transient. This switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. The analog and digital sections of the AD9744 have separate power supply inputs (i.e., AVDD and DVDD) that can operate independently over a 2.7 V to 3.6 V range. The digital section, which is capable of operating at a rate of up to 165 MSPS, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.2 V band gap voltage reference, and a reference control amplifier. The DAC full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET, connected to the full-scale adjust (FS ADJ) pin. The external resistor, in combination with both the reference control amplifier and voltage reference VREFIO, sets the reference current IREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is 32 times IREF. The AD9744 contains an internal 1.2 V band gap reference. The internal reference can be disabled by raising REFLO to AVDD. It can also be easily overridden by an external reference with no effect on performance. REFIO serves as either an input or an output depending on whether the internal or an external reference is used. To use the internal reference, simply decouple the REFIO pin to ACOM with a 0.1 mF capacitor and connect REFLO to ACOM via a resistance less than 5 W. The internal reference voltage will be present at REFIO. If the voltage at REFIO is to be used anywhere else in the circuit, an external buffer amplifier with an input bias current of less than 100 nA should be used. An example of the use of the internal reference is shown in Figure 4. 3.3V OPTIONAL EXTERNAL REF BUFFER REFLO +1.2V REF REFIO 150pF AVDD ADDITIONAL LOAD 0.1 F 2k FS ADJ CURRENT SOURCE ARRAY AD9744 Figure 4. Internal Reference Configuration An external reference can be applied to REFIO, as shown in Figure 5. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 mF compensation capacitor is not required since the internal reference is overridden, and the relatively high input impedance of REFIO minimizes any loading of the external reference. 3.3V AVDD VREFIO REFIO FS ADJ RSET I REF = VREFIO /R SET REFLO 150pF +1.2V REF AVDD EXTERNAL REF CURRENT SOURCE ARRAY REFERENCE CONTROL AMPLIFIER AD9744 Figure 5. External Reference Configuration -10- REV. A AD9744 REFERENCE CONTROL AMPLIFIER The AD9744 contains a control amplifier that is used to regulate the full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter, as shown in Figure 4, so that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied to the segmented current sources with the proper scale factor to set IOUTFS, as stated in Equation 3. The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 mA and 625 mA. The wide adjustment span of IOUTFS provides several benefits. The first relates directly to the power dissipation of the AD9744, which is proportional to IOUTFS (refer to the Power Dissipation section). The second relates to the 20 dB adjustment, which is useful for system gain control purposes. The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency small signal multiplying applications. DAC TRANSFER FUNCTION Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be expressed as VDIFF = (2 DAC CODE - 16383) / 16384 (32 RLOAD / RSET ) VREFIO { } (8) Equations 7 and 8 highlight some of the advantages of operating the AD9744 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTA and IOUTB, such as noise, distortion, and dc offsets. Second, the differential code dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (i.e., VOUTA or VOUTB), thus providing twice the signal power to the load. Note that the gain drift temperature performance for a singleended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9744 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship, as shown in Equation 8. ANALOG OUTPUTS Both DACs in the AD9744 provide complementary current outputs, IOUTA and IOUTB. IOUTA provides a near fullscale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 16383), while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as IOUTB = (16383 - DAC CODE ) / 16384 IOUTFS IOUTA = (DAC CODE / 16384) IOUTFS (1) (2) The complementary current outputs in each DAC, IOUTA, and IOUTB may be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equations 5 through 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB, can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9744 is optimum and specified using a differential transformer-coupled output in which the voltage swing at IOUTA and IOUTB is limited to 0.5 V. The distortion and noise performance of the AD9744 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude decreases. This is due to the first order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Since the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer will allow the AD9744 to provide the required power and voltage levels to different loads. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kW in parallel with 5 pF. It is also slightly dependent on the output voltage (i.e., VOUTA and VOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration will result in the optimum dc linearity. Note that the INL/DNL specifications for the AD9744 are measured with IOUTA maintained at a virtual ground via an op amp. where DAC CODE = 0 to 16383 (i.e., decimal representation). As mentioned previously, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage, VREFIO, and external resistor, RSET. It can be expressed as IOUTFS = 32 IREF where IREF = VREFIO / RSET (3) (4) The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, that are tied to analog common, ACOM. Note that RLOAD may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 W or 75 W cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply VOUTA = IOUTA RLOAD (5) (6) VOUTB = IOUTB RLOAD Note that the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. VDIFF = (IOUTA - IOUTB) RLOAD (7) REV. A -11- AD9744 IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of -1 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9744. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA. The optimum distortion performance for a singleended or differential output is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed 0.5 V. DIGITAL INPUTS LFCSP Package A configurable clock input is available in the LFCSP package, which allows for one single-ended and two differential modes. The mode selection is controlled by the CMODE input, as summarized in Table I. Connecting CMODE to CLKCOM selects the single-ended clock input. In this mode, the CLK+ input is driven with rail-to-rail swings and the CLK- input is left floating. If CMODE is connected to CLKVDD, the differential receiver mode is selected. In this mode, both inputs are high impedance. The final mode is selected by floating CMODE. This mode is also differential, but internal terminations for positive emittercoupled logic (PECL) are activated. There is no significant performance difference among any of the three clock input modes. Table I. Clock Mode Selection The AD9744 digital section consists of 14 input bit channels and a clock input. The 14-bit parallel data inputs follow standard positive binary coding, where DB13 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. DVDD CMODE Pin CLKCOM CLKVDD Float Clock Input Mode Single-Ended Differential PECL The single-ended input mode operates in the same way as the CLOCK input in the 28-lead packages, as described previously. In the differential input mode, the clock input functions as a high impedance differential pair. The common-mode level of the CLK+ and CLK- inputs can vary from 0.75 V to 2.25 V, and the differential voltage can be as low as 0.5 V p-p. This mode can be used to drive the clock with a differential sine wave since the high gain bandwidth of the differential inputs will convert the sine wave into a single-ended square wave internally. The final clock mode allows for a reduced external component count when the DAC clock is distributed on the board using PECL logic. The internal termination configuration is shown in Figure 7. These termination resistors are untrimmed and can vary up to 20%. However, matching between the resistors should generally be better than 1% AD9744 CLK+ CLK- 50 50 CLOCK RECEIVER TO DAC CORE DIGITAL INPUT Figure 6. Equivalent Digital Input The digital interface is implemented using an edge-triggered master/slave latch. The DAC output updates on the rising edge of the clock and is designed to support a clock rate as high as 165 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulsewidth. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. CLOCK INPUT SOIC/TSSOP Packages VTT = 1.3V NOM The 28-lead package options have a single-ended clock input (CLOCK) that must be driven to rail-to-rail CMOS levels. The quality of the DAC output is directly related to the clock quality, and jitter is a key concern. Any noise or jitter in the clock will translate directly into the DAC output. Optimal performance will be achieved if the CLOCK input has a sharp rising edge, since the DAC latches are positive edge triggered. Figure 7. Clock Termination in PECL Mode DAC TIMING Input Clock and Data Timing Relationship Dynamic performance in a DAC is dependent on the relationship between the position of the clock edges and the time at -12- REV. A AD9744 which the input data changes. The AD9744 is rising edge triggered, and so exhibits dynamic performance sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9744 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 8 shows the relationship of SFDR to clock placement with different sample rates. Note that at the lower sample rates, more tolerance is allowed in clock placement, while at higher rates, more care must be taken. 75 35 30 25 IAVDD (mA) 20 15 10 70 65 60 dB 0 20MHz SFDR 2 4 6 8 10 12 IOUTFS (mA) 14 16 18 20 55 50MHz SFDR 50 45 40 50MHz SFDR -2 -1 0 ns 1 2 3 Figure 9. IAVDD vs. IOUTFS 16 14 12 10 8 6 65MSPS 4 125MSPS 165MSPS Figure 8. SFDR vs. Clock Placement @ fOUT = 20 MHz and 50 MHz Sleep Mode Operation The AD9744 has a power-down function that turns off the output current and reduces the supply current to less than 6 mA over the specified supply range of 2.7 V to 3.6 V and temperature range. This mode can be activated by applying a logic level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 AVDD. This digital input also contains an active pulldown circuit that ensures that the AD9744 remains enabled if this input is left disconnected. The AD9744 takes less than 50 ns to power down and approximately 5 ms to power back up. POWER DISSIPATION IDVDD (mA) 35 -3 2 0 0.01 0.1 RATIO (f OUT /f CLOCK) 1 Figure 10. IDVDD vs. Ratio @ DVDD = 3.3 V 10 9 8 DIFF 7 PECL ICLKVDD (mA) The power dissipation, PD, of the AD9744 is dependent on several factors that include: The power supply voltages (AVDD, CLKVDD, and DVDD) The full-scale current output IOUTFS The update rate fCLOCK The reconstructed digital input waveform 6 5 4 3 2 1 0 0 50 100 150 200 SE The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS, as shown in Figure 9, and is insensitive to fCLOCK. Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figure 10 shows IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 3.3 V. fCLOCK (MSPS) Figure 11. ICLKVDD vs. fCLOCK and Clock Mode REV. A -13- AD9744 APPLYING THE AD9744 Output Configurations DIFFERENTIAL COUPLING USING AN OP AMP The following sections illustrate some typical output configurations for the AD9744. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting within the bandwidth of the chosen op amp. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to an appropriately sized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground. DIFFERENTIAL COUPLING USING A TRANSFORMER An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 13. The AD9744 is configured with two equal load resistors, RLOAD, of 25 W. The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp's distortion performance by preventing the DAC's high slewing output from overloading the op amp's input. 500 AD9744 IOUTA 22 225 225 IOUTB 21 COPT 500 25 25 AD8047 Figure 13. DC Differential Coupling Using an Op Amp An RF transformer can be used to perform a differential-to-singleended signal conversion, as shown in Figure 12. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer's pass band. An RF transformer, such as the Mini-Circuits T1-1T, provides excellent rejection of commonmode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes. Note that the transformer provides ac coupling only. MINI-CIRCUITS T1-1T The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide some additional signal gain. The op amp must operate off a dual supply since its output is approximately 1 V. A high speed amplifier capable of preserving the differential performance of the AD9744 while meeting other system level objectives (e.g., cost or power) should be selected. The op amp's differential gain, gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. The differential circuit shown in Figure 14 provides the necessary level shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9744 and the op amp, is also used to level-shift the differential output of the AD9744 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. 500 IOUTA 22 AD9744 IOUTB 21 OPTIONAL RDIFF RLOAD AD9744 IOUTA 22 225 225 IOUTB 21 COPT AD8041 1k AVDD Figure 12. Differential Output Using a Transformer The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9744. A differential resistor, RDIFF, may be inserted in applications where the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer's impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF. 25 25 1k Figure 14. Single Supply DC Differential Coupled Circuit SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT Figure 15 shows the AD9744 configured to provide a unipolar output range of approximately 0 V to 0.5 V for a doubly terminated 50 W cable since the nominal full-scale current, IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 W. In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different -14- REV. A AD9744 values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL), discussed in the Analog Output section. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested. AD9744 IOUTA 22 50 IOUTB 21 25 80 75 IOUTFS = 20mA VOUTA = 0V TO 0.5V 50 This is referred to as the power supply rejection ratio (PSRR). For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with the DAC's full-scale current, IOUTFS. AC noise on the dc supplies is common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise will occur over the spectrum from tens of kHz to several MHz. The PSRR versus frequency of the AD9744 AVDD supply over this frequency range is shown in Figure 17. 85 Figure 15. 0 V to 0.5 V Unbuffered Voltage Output 70 SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION PSRR (dB) 65 60 55 50 45 40 Figure 16 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9744 output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, minimizing the nonlinear output impedance effect on the DAC's INL performance as described in the Analog Output section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by U1's slew rate capabilities. U1 provides a negative unipolar output voltage, and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output should be set within U1's voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance may result with a reduced IOUTFS since the signal current U1 will be required to sink less signal current. COPT RFB 200 0 2 6 4 8 FREQUENCY (MHz) 10 12 Figure 17. Power Supply Rejection Ratio (PSRR) AD9744 IOUTA 22 IOUTFS = 10mA U1 IOUTB 21 200 VOUT = IOUTFS R FB Note that the ratio in Figure 17 is calculated as amps out/volts in. Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. The voltage noise on AVDD, therefore, will be added in a nonlinear manner to the desired IOUT. Due to the relative different size of these switches, the PSRR is very code dependent. This can produce a mixing effect that can modulate low frequency power supply noise to higher frequencies. Worst-case PSRR for either one of the differential DAC outputs will occur when the full-scale current is directed toward that output. As a result, the PSRR measurement in Figure 17 represents a worst-case condition in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured. An example serves to illustrate the effect of supply noise on the analog supply. Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV of noise and, for simplicity's sake (ignoring harmonics), all of this noise is concentrated at 250 kHz. To calculate how much of this undesired noise will appear as current noise superimposed on the DAC's full-scale current, IOUTFS, one must determine the PSRR in dB using Figure 17 at 250 kHz. To calculate the PSRR for a given RLOAD, such that the units of PSRR are converted from A/V to V/V, adjust the curve in Figure 17 by the scaling factor 20 log (RLOAD). For instance, if RLOAD is 50 W, the PSRR is reduced by 34 dB (i.e., PSRR of the DAC at 250 kHz, which is 85 dB in Figure 17, becomes 51 dB VOUT/VIN). Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9744 features separate analog and digital supplies and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip Figure 16. Unipolar Buffered Voltage Output POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION Many applications seek high speed and high performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the printed circuit board is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing as well as power supply bypassing and grounding to ensure optimum performance. Figures 21 to 24 illustrate the recommended printed circuit board ground, power, and signal plane layouts implemented on the AD9744 evaluation board. One factor that can measurably affect system performance is the ability of the DAC output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. REV. A -15- AD9744 as physically possible. Similarly, DVDD, the digital supply, should be decoupled to DCOM as close to the chip as physically possible. For those applications that require a single 3.3 V supply for both the analog and digital supplies, a clean analog supply may be generated using the circuit shown in Figure 18. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained by using low ESR type electrolytic and tantalum capacitors. FERRITE BEADS TTL/CMOS LOGIC CIRCUITS AVDD 100 F ELECT. 10 F-22 F TANT. 0.1 F CER. ACOM EVALUATION BOARD General Description The TxDAC family evaluation boards allow for easy setup and testing of any TxDAC product in the SOIC and LFCSP packages. Careful attention to layout and circuit design, combined with a prototyping area, allows the user to evaluate the AD9744 easily and effectively in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9744 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single and differential outputs. The digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to operate the AD9744 with either the internal or external reference or to exercise the power-down feature. 3.3V POWER SUPPLY Figure 18. Differential LC Filter for Single 3.3 V Applications J1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X JP3 CKEXTX 1 DCOM 10 R9 DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X CKEXTX 1 RP3 2 RP3 3 RP3 4 RP3 5 RP3 6 RP3 7 RP3 8 RP3 1 RP4 2 RP4 3 RP4 4 RP4 5 RP4 6 RP4 7 RP4 22 16 22 15 22 14 22 13 22 12 22 11 22 10 22 9 22 16 22 15 22 14 22 13 22 12 22 11 22 10 22 9 10 R9 2 R1 3 R2 4 R3 5 R4 6 R5 7 R6 8 R7 9 R8 2 R1 3 R2 4 R3 5 R4 6 R5 7 R6 8 R7 9 R8 RP5 OPT 1 DCOM RP1 OPT DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CKEXT RIBBON 8 RP4 1 2 1 3 5 2 3 6 5 9 6 8 4 7 4 R9 10 7 8 9 DCOM L2 TB1 1 C7 0.1 F TB1 2 BEAD RED TP2 DVDD + C4 10 F 25V BLK TP4 C6 0.1 F BLK TP7 BLK TP8 L3 TB1 3 C9 0.1 F TB1 4 BEAD RED TP5 AVDD + C5 10 F 25V BLK TP6 C8 0.1 F BLK TP10 BLK TP9 Figure 19. SOIC Evaluation Board--Power Supply and Digital Inputs -16- DCOM RP6 OPT R9 10 RP2 OPT R3 R7 R3 R1 R8 R1 R7 R5 R6 R5 R2 R4 R2 R4 R6 R8 REV. A AD9744 AVDD + C14 10 F 16V C16 0.1 F C17 0.1 F CUT UNDER DUT JP6 DVDD + C15 10 F 16V C18 0.1 F C19 0.1 F R5 OPT CLOCK CKEXT JP4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CLOCK TP1 WHT DVDD JP2 AVDD MODE R6 OPT 3 2 1 T1-1T REF TP3 WHT C1 0.1 F C2 0.1 F T1 4 5 6 S3 R4 50 R2 10k S5 DVDD C13 OPT DVDD IX S2 IOUTA 1 JP10 AB 2 3 R11 50 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CLOCK DVDD DCOM MODE AVDD RESERVED IOUTA U1 AD9744 IOUTB ACOM NC FS ADJ REFIO REFLO SLEEP JP8 IOUT R1 2k C11 0.1 F AVDD C12 OPT JP9 AVDD 2 AB 3 1 EXT JP5 INT REF SLEEP TP11 WHT R3 10k S1 IOUTB R10 50 IY 1 2 AB 3 JP11 Figure 20. SOIC Evaluation Board--Output Signal Conditioning REV. A -17- AD9744 Figure 21. SOIC Evaluation Board-Primary Side Figure 22. SOIC Evaluation Board--Secondary Side -18- REV. A AD9744 Figure 23. SOIC Evaluation Board-Ground Plane Figure 24. SOIC Evaluation Board--Power Plane REV. A -19- AD9744 Figure 25. SOIC Evaluation Board Assembly--Primary Side Figure 26. SOIC Evaluation Board Assembly--Secondary Side -20- REV. A AD9744 L1 BEAD TB1 1 C3 0.1 F TB1 2 BLK TP2 C2 10 F 6.3V C10 0.1 F RED TP12 CVDD 2 4 6 8 10 12 L2 BEAD TB3 1 C7 0.1 F TB3 2 RED TP5 AVDD C9 0.1 F TB4 2 BLK TP6 C5 10 F 6.3V C8 0.1 F BLK TP4 C4 10 F 6.3V C6 0.1 F RED TP13 DVDD 14 16 18 20 22 24 26 28 30 32 34 36 38 40 J1 L3 BEAD TB4 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 JP3 CKEXTX DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X R3 100 DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X R4 100 R15 100 R16 100 R17 100 R18 100 R19 100 R20 100 1 RP3 2 RP3 3 RP3 4 RP3 5 RP3 6 RP3 7 RP3 8 RP3 1 RP4 2 RP4 3 RP4 4 RP4 5 RP4 6 RP4 7 RP4 8 RP4 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CKEXT CKEXTX R21 100 R24 100 R25 100 R26 100 R27 100 R28 100 Figure 27. LFCSP Evaluation Board Schematic--Power Supply and Digital Inputs REV. A -21- HEADER STRAIGHT UP MALE NO SHROUD AD9744 AVDD SLEEP TP11 WHT C17 0.1 F DVDD C19 0.1 F CVDD C32 0.1 F R29 10k DB7 DB6 DVDD DB5 DB4 DB3 DB2 DB1 DB0 CVDD CLK CLKB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CMODE 16 DB7 DB6 DVDD DB5 DB4 DB3 DB2 DB1 DB0 DCOM U1 CVDD CLK CLKB CCOM CMODE MODE DB8 DB9 DB10 DB11 DB12 DB13 DCOM1 SLEEP FS ADJ REFIO ACOM IA IB ACOM1 AVDD AVDD1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DB8 DB9 DB10 DB11 DB12 DB13 TP3 WHT TP1 WHT 3 2 1 AVDD C11 0.1 F T1-1T JP9 T1 4 5 6 S3 AGND: 3, 4, 5 R11 50 DNP C13 JP8 IOUT AD9744LFCSP TP7 WHT R30 10k JP1 MODE CVDD DNP C12 R1 2k 0.1% R10 50 Figure 28. LFCSP Evaluation Board Schematic--Output Signal Conditioning 1 7 U4 2 AGND: 5 CVDD: 8 CVDD CVDD C20 10 F 16V C35 0.1 F R5 120 CLKB JP2 CKEXT CLK 3 U4 4 AGND: 5 CVDD: 8 C34 0.1 F 6 S5 AGND: 3, 4, 5 R6 50 R2 120 Figure 29. LFCSP Evaluation Board Schematic--Clock Input -22- REV. A AD9744 Figure 30. LFCSP Evaluation Board Layout--Primary Side Figure 31. LFCSP Evaluation Board Layout--Secondary Side REV. A -23- AD9744 Figure 32. LFCSP Evaluation Board Layout--Ground Plane Figure 33. LFCSP Evaluation Board Layout--Power Plane -24- REV. A AD9744 Figure 34. LFCSP Evaluation Board Layout Assembly--Primary Side Figure 35. LFCSP Evaluation Board Layout Assembly--Secondary Side REV. A -25- AD9744 OUTLINE DIMENSIONS 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 9.80 9.70 9.60 28 15 4.50 4.40 4.30 1 14 6.40 BSC PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX COPLANARITY 0.10 SEATING PLANE 0.20 0.09 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AE 28-Lead Standard Small Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches) 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 1 14 10.65 (0.4193) 10.00 (0.3937) 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 8 0 1.27 (0.0500) 0.51 (0.0201) SEATING 0.32 (0.0126) BSC 0.33 (0.0130) PLANE 0.23 (0.0091) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 32-Lead Lead Frame Chip Scale Package [LFCSP] (CP-32) Dimensions shown in millimeters 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 24 32 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ 0.50 BSC BOTTOM VIEW 3.25 3.10 SQ 2.95 8 0.50 0.40 0.30 12 MAX 1.00 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 17 16 9 3.50 REF 1.00 0.90 0.80 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 -26- REV. A AD9744 Revision History Location 5/03--Data Sheet changed from REV. 0 to REV. A. Page Added 32-Lead LFCSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UNIVERSAL Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Edits to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Replaced TPCs 1, 4, 7, and 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Edits to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edits to FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Added CLOCK INPUT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Added new Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Edits to DAC TIMING section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Edits to Sleep Mode Operation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Edits to POWER DISSIPATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Renumbered Figures 8-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Added Figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Added Figures 27-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 REV. A -27- -28- C02913-0-5/03(A) |
Price & Availability of AD9744ACP-PCB
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